The present invention relates to improving the accuracy of simulations that are used to predict the electrical behavior of integrated circuits.
Simulations are used by engineers to predict the expected electrical behavior of electronic circuits and systems, such as integrated circuits. In the example of integrated circuits, a circuit description such as a netlist of an integrated circuit, or more likely, an integrated circuit portion, is input as a database to a simulator. The simulator accesses a library of models and substitutes the models for devices in the netlist. The simulator also receives a number input signals or vectors from an engineer, software generator, or other source. The simulator program then predicts the expected response of the integrated circuit or portion to the input vectors.
Many errors can reduce the accuracy of these models and thereby reduce the accuracy of simulation results. One group of errors may be referred to as pattern dependent effects. These effects can be quite noticeable, particularly on the gate length of a MOSFET device or emitter of a bipolar transistor.
The location of a gate of a MOSFET device relative to other gates on an integrated circuit layout can influence its length after device manufacturing. For example, the geometries of these devices have become so small that they are approaching the wavelength of the light used to expose resist that is used to define the pattern of layers, such as polysilicon gates, on an integrated circuit during its manufacturing. This and related phenomena are referred to as optical proximity effects. Also, after exposed resist is removed, the etch used to remove unprotected polysilicon etches differently in larger areas of unprotected polysilicon than it does in tighter quarters—this is referred to as etch bias. These effects can be somewhat predicted and countered when integrated circuit masks are made by using an optical correction algorithm, though residual errors continue to exist.
Conventional solutions that reduce these effects include, depending on circumstances, using so called matching “dummies,” making devices larger, and complicated layout methods such as quad connections. Each of these increase the size of a layout of a circuit and consume valuable die real estate.
If the above effects could be modeled accurately, the use of these techniques could be limited to instances where it is shown by simulation to be sufficiently important. Accordingly, what is needed are methods, software, and apparatus to more accurately simulate an integrated circuit or integrated circuit portion by including these pattern dependent effects.